Name
Title | ||
|---|---|---|
A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach |
Abstract | ||
|---|---|---|
This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1驴 CMOS ASIC technology. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/12.485568 | Computers, IEEE Transactions |
Keywords | Field | DocType |
CMOS integrated circuits,VLSI,adders,digital arithmetic,multiplying circuits,1 μ CMOS ASIC technology,1 micron,algorithmic approach,fast parallel multipliers,logic synthesis tools,partial product reduction tree,silicon compilation,speed optimized partial product reduction | Logic synthesis,Computer science,Parallel algorithm,Parallel computing,CMOS,Multiplier (economics),Application-specific integrated circuit,Wallace tree,Integrated circuit,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
45 | 3 | 0018-9340 |
Citations | PageRank | References |
131 | 16.48 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vojin G. Oklobdzija | 1 | 806 | 137.25 |
| David Villeger | 2 | 194 | 31.07 |
| Simon S. Liu | 3 | 131 | 16.48 |