Name
Title | ||
|---|---|---|
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology |
Abstract | ||
|---|---|---|
In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/92.386228 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
faster multiplier,parallel multiplier,uneven input arrival time,column compressor,improved column compression tree,final adder,longest signal path,propagate adder,uneven signal arrival profile,column compressors configuration,improving multiplier design,optimized final adder,cmos technology,multiplier tree,adders,logic design,design optimization,compressors | Logic synthesis,Compression (physics),Adder,Computer science,Multiplier (economics),CMOS,Electronic engineering,Serial binary adder,Gas compressor,Carry-save adder,Computer hardware | Journal |
Volume | Issue | ISSN |
3 | 2 | 1524-766X |
Citations | PageRank | References |
54 | 11.70 | 6 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vojin G. Oklobdzija | 1 | 806 | 137.25 |
| David Villeger | 2 | 194 | 31.07 |