Hsiu-Chuan Shih - Citegraph

Author Info

Name	Affiliation	Papers
HSIU-CHUAN SHIH	National Tsing Hua University, Hsinchu, Taiwan	6
Collaborators	Citations	PageRank
31	6	2.22
Referers	Referees	References
50	192	36

Search Limit

100192

Publications (6 rows)

Collaborators (31 rows)

Referers (50 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.	0	0.34	2017
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs	1	0.36	2015
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool	3	0.46	2014
An enhanced double-TSV scheme for defect tolerance in 3D-IC	0	0.34	2013
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs	0	0.34	2013
Training-Based Forming Process For Rram Yield Improvement	2	0.39	2011

1