Paper Info
Title
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool
Abstract
DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.
Year
DOI
Venue
2014
10.1109/TCAD.2014.2323203
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
architecture exploration,component-based modeling approach,performance estimation,timing circuits,integrated circuit modelling,DRAM area power timing,DRAM architecture exploration,3-D DRAM,array assembly,interface customization,DRAM chips,modeling and simulation,flexible electronics,DRAM,3D stacked DRAM,timing modeling tool
Journal
33
Issue
ISSN
Citations 
9
0278-0070
3
PageRank 
References 
Authors
0.46
0
8
Name
Order
Citations
PageRank
Hsiu-Chuan Shih162.22
Pei-Wen Luo2748.22
Jen-Chieh Yeh322321.72
Shu-Yen Lin49413.01
Ding-Ming Kwai552146.85
Shih-Lien Lu630.46
Andre Schaefer730.46
Wu, Cheng-Wen81843170.44