Title
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
Abstract
Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and <;10ns read latency on a 45nm DRAM process. The architecture is based on small subarrays with short WL and BL to realize the low latency and energy efficiency. We also integrated several circuit techniques, including adaptive power to speed-up access time and banks rotation to reduce thermal issues. The proposed device is also estimated in a system simulation that shows that the power efficiency is higher than comparable systems.
Year
DOI
Venue
2015
10.1109/VLSIC.2015.7231256
2015 Symposium on VLSI Circuits (VLSI Circuits)
Keywords
Field
DocType
16 channel DRAM,3D stacked memory device,TSV,computer-aided design methodology,energy efficiency,thermal issue reduction,dynamic random-access memory,through silicon via,size 45 nm
Dram,Electrical efficiency,Access time,Latency (engineering),Computer science,Parallel computing,Communication channel,Electronic engineering,Bandwidth (signal processing),Latency (engineering),CAS latency
Conference
ISSN
ISBN
Citations 
2158-5601
978-4-86348-502-0
1
PageRank 
References 
Authors
0.36
4
21
Name
Order
Citations
PageRank
Pei-Wen Luo1748.22
Chi-Kang Chen242.45
Yu-Hui Sung310.36
Wu Wei420414.84
Hsiu-Chuan Shih562.22
Chia-Hsin Lee6245.29
Kuo-Hua Lee710.36
Ming-Wei Li810.36
Mei-Chiang Lung910.36
Chun-Nan Lu1010.36
Yung-Fa Chou1124423.76
Po-Lin Shih1210.36
Chung-Hu Ke1310.36
Chun Shiah1411.71
Patrick Stolt1510.36
shigeki tomishima16152.42
Ding-Ming Kwai1752146.85
Bor-Doou Rong1811.37
Nicky Lu1912.05
Shih-Lien Lu2095867.34
Wu, Cheng-Wen211843170.44