MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects | 1 | 0.36 | 2014 |
FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only) | 0 | 0.34 | 2010 |
On the Effects of Process Variation in Network-on-Chip Architectures | 36 | 1.07 | 2010 |
Performance And Power Optimization Through Data Compression In Network-On-Chip Architectures | 44 | 1.74 | 2008 |
MIRA: A Multi-layered On-Chip Interconnect Router Architecture | 102 | 3.92 | 2008 |
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects | 27 | 1.32 | 2007 |
Exploring Fault-Tolerant Network-on-Chip Architectures | 121 | 3.62 | 2006 |
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks | 101 | 4.09 | 2006 |
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks | 39 | 1.65 | 2006 |
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects | 5 | 0.51 | 2006 |
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers | 145 | 6.27 | 2006 |
A low latency router supporting adaptivity for on-chip interconnects | 129 | 5.01 | 2005 |
Design and analysis of an NoC architecture from performance, reliability and energy perspective | 56 | 1.93 | 2005 |