Paper Info
Title
Performance And Power Optimization Through Data Compression In Network-On-Chip Architectures
Abstract
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache banks interconnected through a packet-based Network-on-Chip (NoC) communication fabric. Thus, the NoC plays a critical role in optimizing the performance and power consumption of such non-uniform cache-based multicore architectures. While almost all prior NoC studies have focused on the design of router microarchitectures for achieving this goal, in this paper we explore the role of data compression on NoC performance and energy behavior In this context, we examine two different configurations that explore combinations of storage and communication compression: (1) Cache Compression (CC) and (2) Compression in the NIC (NC). We also address techniques to hide the decompression latency by overlapping with NoC communication latency. Our simulation results with a diverse set of scientific and commercial benchmark traces reveal that CC can provide up to 33% reduction in network latency and up to 23% power savings. Even in the case of NC - where the data is compressed only when passing through the NoC fabric of the NUCA architecture and stored uncompressed - performance and power savings of up to 32% and 21%, respectively, can be obtained. These performance benefits in the interconnect translate up to 17% reduction in CPI. These benefits are orthogonal to any router architecture and make a strong case for utilizing compression for optimizing the performance and power envelope of NoC architectures. In addition, the study demonstrates the criticality of designing faster routers in shaping the performance behavior.
Year
DOI
Venue
2008
10.1109/HPCA.2008.4658641
2008 IEEE 14TH INTERNATIONAL SYMPOSIUM ON HIGH PEFORMANCE COMPUTER ARCHITECTURE
Keywords
Field
DocType
power optimization,data compression,network on chip,system on a chip,compaction,chip,computer architecture,network routing
Power optimization,System on a chip,Computer science,Cache,Network packet,Parallel computing,Network on a chip,Real-time computing,Router,Data compression,Multi-core processor,Embedded system
Conference
ISSN
Citations 
PageRank 
1530-0897
44
1.74
References 
Authors
23
8
Name
Order
Citations
PageRank
Reetuparna Das1111747.07
Asit K. Mishra2121646.21
Chrysostomos Nicopoulos383550.37
Dongkook Park480631.84
Narayanan Vijaykrishnan56955524.60
Ravishankar Iyer672035.52
Mazin S. Yousif732120.66
Chita R. Das8104645.21