Paper Info
Title
A low latency router supporting adaptivity for on-chip interconnects
Abstract
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits fromcongestionaware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs.
Year
DOI
Venue
2005
10.1145/1065579.1065726
DAC
Keywords
Field
DocType
low latency,energy consumption,two-stage pipelined architecture use,low latency router,router architecture,on-chip interconnects,routing algorithm benefit,better routing decision,adaptive routing,noc routing algorithm,noc design,proposed architecture,integrated circuit design,system on chip,chip,network latency,system on a chip,routing,switches,chip scale packaging,interconnection,network on chip,look ahead,flow control,networks,network on a chip,network routing
Multipath routing,Equal-cost multi-path routing,Link-state routing protocol,Dynamic Source Routing,Enhanced Interior Gateway Routing Protocol,Static routing,Computer science,Policy-based routing,Real-time computing,Routing table
Conference
ISSN
ISBN
Citations 
0738-100X
1-59593-058-2
129
PageRank 
References 
Authors
5.01
11
5
Search Limit
100129
Name
Order
Citations
PageRank
Jongman Kim177037.65
Dongkook Park280631.84
T. Theocharides349524.54
Narayanan Vijaykrishnan46955524.60
Chita R. Das5146780.03