Paper Info
Title
Energy Efficient Architecture for Graph Analytics Accelerators.
Abstract
Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area.
Year
DOI
Venue
2016
10.1109/ISCA.2016.24
ISCA
Keywords
Field
DocType
Hardware accelerators,graph analytics,energy efficient architectures,architectures for emerging applications
Logic synthesis,Electrical efficiency,Convergence (routing),Data structure,Computer architecture,Computer science,Instruction set,Parallel computing,High-level synthesis,SystemC,Bandwidth (signal processing)
Conference
ISSN
ISBN
Citations 
1063-6897
978-1-4673-8948-8
19
PageRank 
References 
Authors
0.61
27
7
Name
Order
Citations
PageRank
Muhammet Mustafa Ozdal131323.18
Serif Yesil2190.61
Taemn Kim338228.18
Andrey Ayupov41127.12
John Greth5190.61
Steven M. Burns6563104.03
Özcan Özturk7303.82