| A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power | 15 | 0.71 | 2011 |
| Low-Power Divider Retiming in a | 1 | 0.35 | 2011 |
| Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. | 2 | 0.36 | 2011 |
| AD-PLL for WiMAX with digitally-regulated TDC and glitch correction logic | 0 | 0.34 | 2010 |
| Noise analysis and minimization in bang-bang digital PLLs | 37 | 2.24 | 2009 |
| An all-digital architecture for low-jitter regulated delay lines. | 1 | 0.48 | 2009 |
