Name
Abstract | ||
|---|---|---|
This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3- 3.8GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase detector and a digital loop filter to further take advantage of the digital approach. The most important source of spurs is identified in the time skew between counter and TDC in the PLL. This mechanism gives rise to a glitch in the digital feedback signal and spurs in the output spectrum. A simple glitch-corrector logic is described, that completely removes this effect, thus allowing to meet the phase noise specifications. The AD-PLL has been designed in a 90nm CMOS process. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1155/2010/175764 | Eurasip Journal on Embedded Systems |
Keywords | Field | DocType |
delay-locked loop,output spectrum,cmos process,digitally-regulated tdc,in-band noise,pll output,lead-lag phase detector,digital feedback signal,glitch correction logic,digital loop filter,digital approach,digital converter | Phase-locked loop,Glitch,Wireless,Computer science,Real-time computing,WiMAX,Electronic engineering,Bandwidth (signal processing),Digital converter | Journal |
Volume | Issue | ISSN |
2010, | 175764 | 1687-3955 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Salvatore Levantino | 1 | 351 | 43.23 |
| Marco Zanuso | 2 | 152 | 14.89 |
| Paolo Madoglio | 3 | 91 | 13.34 |
| Davide Tasca | 4 | 56 | 4.48 |
| Carlo Samori | 5 | 349 | 39.76 |
| Andrea L. Lacaita | 6 | 320 | 42.41 |