Name
Abstract | ||
|---|---|---|
The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to fail to lock or to degrade jitter at certain synthesized frequencies. This brief proposes a novel automatic retiming circuit, which mitigates metasta... |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCSII.2011.2124510 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Delay,Phase locked loops,Voltage-controlled oscillators,Frequency conversion,Jitter,Calibration,Phase noise | Journal | 58 |
Issue | ISSN | Citations |
4 | 1549-7747 | 1 |
PageRank | References | Authors |
0.35 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Davide Tasca | 1 | 56 | 4.48 |
| Marco Zanuso | 2 | 152 | 14.89 |
| Salvatore Levantino | 3 | 351 | 43.23 |
| Carlo Samori | 4 | 349 | 39.76 |
| Andrea L. Lacaita | 5 | 320 | 42.41 |