| Near-optimal replacement policies for shared caches in multicore processors | 0 | 0.34 | 2021 |
| Exposing Abstraction-Level Interactions with a Parallel Ray Tracer | 0 | 0.34 | 2019 |
| Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding | 0 | 0.34 | 2019 |
| ReD: A reuse detector for content selection in exclusive shared last-level caches. | 2 | 0.43 | 2019 |
| Reuse Detector: Improving the Management of STT-RAM SLLCs. | 0 | 0.34 | 2018 |
| Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. | 0 | 0.34 | 2016 |
| ACDC: Small, Predictable and High-Performance Data Cache | 1 | 0.36 | 2015 |
| A predictable hardware to exploit temporal reuse in real-time and embedded systems | 2 | 0.63 | 2015 |
| A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip | 3 | 0.40 | 2014 |
| Dynamic construction of circuits for reactive traffic in homogeneous CMPs | 0 | 0.34 | 2014 |
| Capturing the sensitivity of optical network quality metrics to its network interface parameters. | 1 | 0.36 | 2014 |
| The reuse cache: downsizing the shared last-level cache | 21 | 0.72 | 2013 |
| Exploiting reuse locality on inclusive shared last-level caches | 9 | 0.56 | 2013 |
| Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems | 0 | 0.34 | 2013 |
| Characterization and cost-efficient selection of NoC topologies for general purpose CMPs | 0 | 0.34 | 2013 |
| A Small and Effective Data Cache for Real-Time Multitasking Systems | 0 | 0.34 | 2012 |
| ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache | 15 | 0.63 | 2012 |
| Multi-level Adaptive Prefetching based on Performance Gradient Tracking. | 7 | 0.52 | 2011 |
| Filtering directory lookups in CMPs with write-through caches | 0 | 0.34 | 2011 |
| Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems | 15 | 0.58 | 2011 |
| Filtering directory lookups in CMPs | 0 | 0.34 | 2010 |
| Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems | 8 | 0.47 | 2010 |
| A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors | 4 | 0.41 | 2009 |
| Low-Cost Adaptive Data Prefetching | 2 | 0.41 | 2008 |
| Avoiding the WCET Overestimation on LRU Instruction Cache | 4 | 0.43 | 2008 |
| Selection of the Register File Size and the Resource Allocation Policy on SMT Processors | 2 | 0.37 | 2008 |
| Microarchitectural Support for Speculative Register Renaming | 2 | 0.36 | 2007 |
| Characterization of Apache web server with Specweb2005 | 3 | 0.59 | 2007 |
| Data prefetching in a cache hierarchy with high bandwidth and capacity | 6 | 0.47 | 2007 |
| Speculative early register release | 1 | 0.35 | 2006 |
| Speeding-up synchronizations in DSM multiprocessors | 1 | 0.35 | 2006 |
| Store Buffer Design in First-Level Multibanked Data Caches | 17 | 0.85 | 2005 |
| Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors | 14 | 0.81 | 2005 |
| Contents Management in First-Level Multibanked Data Caches | 2 | 0.40 | 2004 |
| Late Allocation and Early Release of Physical Registers | 12 | 0.56 | 2004 |
| Counteracting Bank Misprediction in Sliced First-Level Caches | 2 | 0.39 | 2003 |
| Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation | 2 | 0.89 | 2003 |
| Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors | 24 | 1.55 | 2003 |
| Hardware Schemes for Early Register Release | 25 | 0.90 | 2002 |
| Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware | 4 | 0.41 | 2001 |
| Modeling load address behaviour through recurrences | 2 | 0.38 | 2000 |
| Dynamic Register Renaming Through Virtual-Physical Registers | 5 | 0.68 | 2000 |
| Characterization and improvement of load/store cache-based prefetching | 8 | 0.53 | 1998 |
| Performance Assessment of Contents Management in Multilevel On-Chip Caches | 1 | 0.36 | 1996 |
