Name
Abstract | ||
|---|---|---|
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic register renaming scheme that delays the allocation of physical registers until a late stage in the pipeline. We show that it can provide important savings in number of physical registers so it can significantly shorter the register file access time. Delaying the allocation of physical registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical registers, which are tags that do not require any storage location. The proposed renaming scheme shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance. |
Year | Venue | Keywords |
|---|---|---|
2000 | J. Instruction-Level Parallelism | register file |
Field | DocType | Volume |
Status register,Register allocation,Computer science,Memory data register,Parallel computing,Control register,Register file,Register renaming,Memory buffer register,Processor register | Journal | 2 |
Citations | PageRank | References |
5 | 0.68 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Teresa Monreal | 1 | 114 | 7.40 |
| Antonio González | 2 | 3178 | 229.66 |
| Mateo Valero | 3 | 4520 | 355.94 |
| José González | 4 | 526 | 35.85 |
| Victor Vinals | 5 | 227 | 21.83 |