Name
Abstract | ||
|---|---|---|
Networks on Chip (NoCs) have a large impact on system performance, area and energy. Considering the characteristics of the memory subsystem while designing the NoC helps identify improvement opportunities and build more efficient designs. Leveraging the frequent request-reply pattern, our proposal dynamically builds the reply path in advance, is able to share circuits between messages, and even removes some implicit replies, significantly reducing NoC latency. A careful implementation of this circuit reservation mechanism achieves an average 17% reduction in router energy consumption, 8% smaller router area and a 2% system performance increase, compared with its baseline counterpart. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.254 | DATE |
Keywords | Field | DocType |
dynamic construction,smaller router area,efficient design,circuit reservation mechanism,system performance,baseline counterpart,router energy consumption,homogeneous cmps,frequent request-reply pattern,system performance increase,noc latency,careful implementation,reactive traffic,routing protocols,coherence,network on chip,noc,computer architecture,routing,integrated circuit design | Reservation,Homogeneous,Computer science,Latency (engineering),Parallel computing,Network on a chip,Real-time computing,Integrated circuit design,Router,Electronic circuit,Energy consumption,Embedded system | Conference |
ISSN | Citations | PageRank |
1530-1591 | 0 | 0.34 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marta Ortín | 1 | 0 | 0.68 |
| Darío Suárez-Gracia | 2 | 76 | 12.06 |
| María Villarroya | 3 | 0 | 0.34 |
| Cruz Izu | 4 | 149 | 23.41 |
| Victor Vinals | 5 | 227 | 21.83 |