Name
Abstract | ||
|---|---|---|
A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low K-VCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-mu m CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm(2). |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transele.E92.C.964 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
phase-locked loop (PLL), self-calibration, low jitter, multi-phase VCO | Journal | E92C |
Issue | ISSN | Citations |
7 | 1745-1353 | 0 |
PageRank | References | Authors |
0.34 | 11 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuo-hsing Cheng | 1 | 325 | 77.87 |
| Yu-Chang Tsai | 2 | 33 | 3.68 |
| Chien-Nan Jimmy Liu | 3 | 97 | 27.07 |
| Kai-Wei Hong | 4 | 17 | 3.34 |
| Chin-Cheng Kuo | 5 | 27 | 4.40 |