Darren Anand - Citegraph

Author Info

Name	Affiliation	Papers
DARREN ANAND	IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452	6
Collaborators	Citations	PageRank
32	15	3.01
Referers	Referees	References
59	109	20

Search Limit

100109

Publications (6 rows)

Collaborators (32 rows)

Referers (59 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory	0	0.34	2019
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming	0	0.34	2018
Embedded DRAM in 45-nm Technology and Beyond	2	0.39	2011
A 45nm Soi Compiled Embedded Dram With Random Cycle Times Down To 1.3ns	2	0.44	2010
Generating At-Speed Array Fail Maps with Low-Speed ATE	4	0.52	2004
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering	7	0.98	2002

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