Name
Abstract | ||
|---|---|---|
In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of stacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under an SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by the gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/92.953496 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
fast heuristic approach,timing-constrained optimization issues,power optimization,dual-supply voltage,gate level power optimization,power consumption,different power consumption,standard cell library,technology-mapped network,timing slack distribution,power/delay model,circuit optimisation,power lower bound,low-power electronics,dual-supply voltages,cmos digital circuits,timing,transitive graphs,constrained f-m algorithm,timing constraints,different timing constraint,maximal-weighted-independent-set problem,vlsi,circuit cad,integrated circuit design,average power improvement,polynomial-time-solvable set problem,possible power penalty,cmos digital integrated circuits,supply voltage,level converters,graph theory,power-delay tradeoff,different supply voltage,level converter,power penalty,sis environment,power reduction,high level synthesis,delay estimation,different supply,low power electronics,polynomial time,semiconductor device modeling,constrained optimization,degradation,voltage,polynomials,cmos technology,indexing terms,constraint optimization,digital circuits,independent set | Power gain,Power optimization,Computer science,Power factor,Electronic engineering,Real-time computing,Standard cell,Electronic circuit,Energy consumption,Switched-mode power supply,Low-power electronics | Journal |
Volume | Issue | ISSN |
9 | 5 | 1063-8210 |
Citations | PageRank | References |
50 | 4.14 | 20 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chunhong Chen | 1 | 176 | 15.66 |
| Ankur Srivastava | 2 | 902 | 79.64 |
| Majid Sarrafzadeh | 3 | 3103 | 317.63 |