Leandro Fiorin - Citegraph

Author Info

Name	Affiliation	Papers
LEANDRO FIORIN	Univ Lugano, Fac Informat, ALaRI, Lugano, Switzerland	28
Collaborators	Citations	PageRank
32	229	17.10
Referers	Referees	References
483	864	398

Search Limit

100864

Publications (28 rows)

Collaborators (32 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Near-Memory Acceleration for Radio Astronomy.	0	0.34	2018
Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing	1	0.34	2017
Sorting big data on heterogeneous near-data processing systems.	0	0.34	2017
An Architecture for Integrated Near-Data Processors.	1	0.35	2017
MeSAP: A fast analytic power model for DRAM memories.	0	0.34	2017
An architecture for near-data processing systems.	3	0.39	2016
Exploring the Design Space of an Energy-Efficient Accelerator for the SKA1-Low Central Signal Processor.	0	0.34	2016
Challenges in exascale radio astronomy: Can the SKA ride the technology wave?	6	0.47	2015
An energy-efficient custom architecture for the SKA1-low central signal processor	6	0.45	2015
Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors.	2	0.41	2014
Fault-Tolerant Network Interfaces for Networks-on-Chip	1	0.38	2014
A Configurable Monitoring Infrastructure for NoC-Based Architectures	1	0.36	2014
Exascale Radio Astronomy: Can We Ride the Technology Wave?	2	0.39	2014
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project	7	0.48	2013
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach	11	0.60	2012
Design of Fault Tolerant Network Interfaces for NoCs	5	0.45	2011
Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?	5	0.49	2011
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors	35	1.10	2011
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips	7	0.55	2011
Hardware-assisted security enhanced Linux in embedded systems: a proposal	1	0.41	2010
A monitoring system for NoCs	2	0.39	2010
MPSoCs run-time monitoring through Networks-on-Chip	14	1.02	2009
Implementation of a reconfigurable data protection module for NoC-based MPSoCs	6	0.64	2008
A security monitoring service for NoCs	32	1.64	2008
An Automated Design Flow for NoC-based MPSoCs on FPGA	11	0.75	2008
Secure Memory Accesses on Networks-on-Chip	38	1.58	2008
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations	18	1.23	2007
A data protection unit for NoC-based architectures	14	0.88	2007