Xiulong Wu - Citegraph

Author Info

Name	Affiliation	Papers
XIULONG WU	Anhui Univ, Sch Elect Sci & Technol, Hefei 230039, Peoples R China	13
Collaborators	Citations	PageRank
34	7	4.65
Referers	Referees	References
31	196	59

Search Limit

100196

Publications (13 rows)

Collaborators (34 rows)

Referers (31 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A New Reading Mode Based On Balanced Pre-Charging And Group Decoding	0	0.34	2020
Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD.	0	0.34	2019
Physical Mechanism Study Of N-Well Doping Effects On The Single-Event Transient Characteristic Of Pmos	0	0.34	2019
An Inverter Chain With Parallel Output Nodes For Eliminating Single-Event Transient Pulse	0	0.34	2019
Picowatt 0.5 V Supply With 3 Ppm/Degrees C Cmos Voltage Reference For Energy Harvesting System	0	0.34	2018
A Dual-Output Hardening Design Of Inverter Chain For P-Hit Single-Event Transient Pulse Elimination	0	0.34	2018
Offset Voltage Suppressed Sense Amplifier With Self-Adaptive Distribution Transformation Technique	0	0.34	2018
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.	1	0.35	2018
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.	2	0.49	2017
A Radiation Harden Enhanced Quatro (Rheq) Sram Cell	2	0.38	2017
Read/Write Margin Enhanced 10t Sram For Low Voltage Application	1	0.36	2016
Analyzing and modeling mobility for infrastructure-less communication	1	0.36	2015
A Compact Equivalent Circuit Model Of Hvldmos And Application In Hivc Design	0	0.34	2006

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