Chung-Wen Huang - Citegraph

Author Info

Name	Affiliation	Papers
CHUNG-WEN HUANG	National Tsing-Hua University, Hsin-Chu, Taiwan	14
Collaborators	Citations	PageRank
24	37	5.91
Referers	Referees	References
93	406	238

Search Limit

100406

Publications (14 rows)

Collaborators (24 rows)

Referers (93 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM	0	0.34	2021
Sparse-Matrix Compression Primitives with OpenCL Framework to Support Halide	0	0.34	2019
Accelerate DNN Performance with Sparse Matrix Compression in Halide	0	0.34	2019
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems	1	0.36	2015
Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs	4	0.39	2014
Programming Model And Tools For Embedded Multicore Systems	0	0.34	2010
Power aware SID-based simulator for embedded multicore DSP subsystems	3	0.38	2010
Support of Paged Register Files for Improving Context Switching on Embedded Processors	0	0.34	2009
Configurable SID-based multi-core simulators for embedded system education	2	0.56	2009
Compilation for compact power-gating controls	12	0.58	2007
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains	3	0.38	2007
System-level design space exploration for security processor prototyping in analytical approaches	1	0.42	2005
A sink-n-hoist framework for leakage power reduction	9	0.77	2005
Power-Aware scheduling for parallel security processors with analytical models	2	0.38	2004

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