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HYUNYOON CHO
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Name
Affiliation
Papers
HYUNYOON CHO
DRAM Design Team, Memory Division, Samsung Electronics, Company, Ltd., Hwasung-city, Gyeonggi-Do, Korea
10
Collaborators
Citations
PageRank
120
110
10.56
Referers
Referees
References
480
235
72
Search Limit
100
480
Publications (10 rows)
Collaborators (100 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
22.2 An 8.5gb/S/Pin 12gb-Lpddr5 Sdram With A Hybrid-Bank Architecture Using Skew-Tolerant, Low-Power And Speed-Boosting Techniques In A 2nd Generation 10nm Dram Process
0
0.34
2020
Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.
0
0.34
2018
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
0
0.34
2017
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices
8
0.42
2017
Understanding power-performance relationship of energy-efficient modern DRAM devices
1
0.35
2017
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures
0
0.34
2017
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture
1
0.35
2017
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
75
6.09
2012
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
18
1.48
2012
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
7
0.52
2011
1