Name
Title | ||
|---|---|---|
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. |
Abstract | ||
|---|---|---|
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with m... |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/JSSC.2011.2164731 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Random access memory,Through-silicon vias,SDRAM,DRAM chips,Silicon,CMOS memory circuits,CMOS integrated circuits | Journal | 47 |
Issue | ISSN | Citations |
1 | 0018-9200 | 75 |
PageRank | References | Authors |
6.09 | 4 | 22 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jung-Sik Kim | 1 | 138 | 11.69 |
| Chi Sung Oh | 2 | 93 | 8.94 |
| Hocheol Lee | 3 | 87 | 7.45 |
| Dong-Hyuk Lee | 4 | 1254 | 48.26 |
| Hyong-Ryol Hwang | 5 | 82 | 6.94 |
| Sooman Hwang | 6 | 82 | 6.61 |
| Byongwook Na | 7 | 83 | 7.99 |
| Joungwook Moon | 8 | 83 | 7.66 |
| Jin-Guk Kim | 9 | 95 | 9.18 |
| Hanna Park | 10 | 82 | 6.94 |
| Jang-Woo Ryu | 11 | 82 | 6.61 |
| Kiwon Park | 12 | 87 | 7.77 |
| Sang-Kyu Kang | 13 | 142 | 12.20 |
| Soyoung Kim | 14 | 168 | 22.15 |
| Hoyoung Kim | 15 | 134 | 12.78 |
| Jong-Min Bang | 16 | 82 | 6.94 |
| Hyunyoon Cho | 17 | 110 | 10.56 |
| Min-Soo Jang | 18 | 97 | 11.05 |
| Cheolmin Han | 19 | 82 | 6.61 |
| Jung-Bae Lee | 20 | 179 | 17.70 |
| Joo-Sun Choi | 21 | 246 | 29.16 |
| Young-Hyun Jun | 22 | 75 | 6.09 |