Konstantinos Masselos

Author Info

Name	Affiliation	Papers
KONSTANTINOS MASSELOS	Univ Peloponnese, Dept Comp Sci & Technol, Tripoli 22100, Greece	32
Collaborators	Citations	PageRank
45	159	18.12
Referers	Referees	References
458	600	262

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100600

Publications (32 rows)

Collaborators (45 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism	0	0.34	2020
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis	0	0.34	2020
Early Evaluation of Implementation Alternatives of Composite Data Structures Toward Maintainability.	0	0.34	2017
A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors.	0	0.34	2017
Compiler-Directed Data Locality Optimization in MATLAB.	0	0.34	2016
Matlab To C Compilation Targeting Application Specific Instruction Set Processors	0	0.34	2016
Automatic Generation of Code Analysis Tools: The CastQL Approach.	0	0.34	2016
Reuse distance analysis for locality optimization in loop-dominated applications	1	0.36	2015
An early memory hierarchy evaluation simulator for multimedia applications	0	0.34	2014
Dynamic source code analysis for memory hierarchy optimization in multimedia applications	4	0.43	2013
MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations	3	0.41	2012
VLSI 2010 Annual Symposium: Selected papers	19	1.41	2011
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation	1	0.39	2011
System Level Design of Complex Hardware Applications Using ImpulseC	2	0.39	2010
Efficient Hardware Looping Units for FPGAs	0	0.34	2010
Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: a geometric programming framework	34	1.66	2009
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs	16	0.95	2008
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework	1	0.37	2008
Outer loop pipelining for application specific datapaths in FPGAs	18	1.16	2008
Prototyping of a WLAN system using C++ based architecture exploration	0	0.34	2007
Automatic On-chip Memory Minimization for Data Reuse	15	0.85	2007
System Level Architecture Exploration for Reconfigurable Systems On Chip	1	0.38	2006
A Comparison Of 2-D Discrete Wavelet Transform Computation Schedules On Fpgas	5	0.65	2006
FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach	9	0.90	2006
Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm	1	0.43	2006
Embedded System Design Using Formal Model Refinement: An Approach Based on the Combined Use of UML and the B Language	2	0.66	2004
Power efficient data path synthesis of sum-of-products computations	2	0.46	2003
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors	5	0.57	2002
Memory Hierarchy Layer Assignment For Data Re-Use Exploitation In Multimedia Algorithms Realized On Predefined Processor Architectures	7	0.56	2001
Strategy for power-efficient design of parallel systems	13	1.06	1999
Novel Codebook Generation Algorithms For Vector Quantization Image Compression	0	0.34	1998
Low-Power Image Decoding Using Fractals	0	0.34	1996