Title
Outer loop pipelining for application specific datapaths in FPGAs
Abstract
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we extend and adapt an existing outer loop pipelining approach known as single dimension software pipelining to generate schedules for field-programmable gate-array (FPGA) hardware coprocessors. Each loop level in nine test loops is pipelined and the resulting schedules are implemented in VHDL and targeted to an Altera Stratix II FPGA. The results show that the fastest solution for all but one of the loops occurs when pipelining is applied one to three levels above the innermost loop. Across the nine test loops we achieve an acceleration over the innermost loop solution of up to seven times, with a mean speedup of 3.2 times. The results suggest that inclusion of outer loop pipelining in future hardware compilers may be worthwhile as it can allow significantly improved results to be achieved at the cost of a small increase in compile time.
Year
DOI
Venue
2008
10.1109/TVLSI.2008.2001744
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
future hardware compiler,test loop,innermost loop,nested loop,loop level,hardware coprocessors,hardware compiler,innermost loop solution,existing outer loop,outer loop,application specific datapaths,hardware description languages,nested loops,schedules,field programmable gate arrays,compile time,software pipelining,coprocessors,vhdl,scheduling,pipelining,field programmable gate array,hardware
Loop fusion,Stratix,Computer science,Loop fission,Loop tiling,Real-time computing,Electronic engineering,Software pipelining,Parallel computing,Loop inversion,VHDL,Embedded system,Nested loop join
Journal
Volume
Issue
ISSN
16
10
1063-8210
Citations 
PageRank 
References 
18
1.16
8
Authors
4
Name
Order
Citations
PageRank
Kieron Turkington1272.40
George A. Constantinides21391160.26
Konstantinos Masselos315918.12
Peter Y. K. Cheung41720208.45