Name
Title | ||
|---|---|---|
Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: a geometric programming framework |
Abstract | ||
|---|---|---|
A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called geometric programming problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performanceoptimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TCAD.2009.2013541 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
off-chip memory access,data-level parallelization,geometric programming framework,FPGA-targeted hardware compilation,on-chip memory utilization,limited on-chip memory resource,loop-level parallelization,memory resources available on-chip,data reuse,accessed data,on-chip memory,nonlinear optimization framework,Combining data reuse | Journal | 28 |
Issue | ISSN | Citations |
3 | 0278-0070 | 34 |
PageRank | References | Authors |
1.66 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qiang Liu | 1 | 160 | 16.34 |
| George A. Constantinides | 2 | 1391 | 160.26 |
| Konstantinos Masselos | 3 | 159 | 18.12 |
| Peter Y. K. Cheung | 4 | 1720 | 208.45 |