Author Info
Name
Affiliation
Papers
ZHAOJI LI
Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Sichuan, Peoples R China
18
Collaborators
Citations 
PageRank 
58
23
7.27
Referers 
Referees 
References 
96
79
33
Title
Citations
PageRank
Year
An Anti-Overcharged High-dV/dt-Immunity Capacitive Level Shifter With Dynamic Discharge Control for Half-Bridge GaN Driver00.342021
Design of an Isolated Circuit Breaker With Robust Interruption Capability for DC Microgrid Protection00.342021
Embedded Hardware Artificial Neural Network Control for Global and Real-Time Imbalance Current Suppression of Parallel Connected IGBTs10.362020
A Neural Network Assistance AMPPT Solar Energy Harvesting System With 89.39% Efficiency and 0.01–0.5% Tracking Errors10.352020
A Novel Virtual Sensing With Artificial Neural Network and K-Means Clustering for IGBT Current Measuring.20.452018
A review of HVI technology.00.342014
Bypass Anode Lateral Igbt On Soi For Snapback Suppression00.342014
Single capacitor with current amplifier compensation for ultra-large capacitive load three-stage amplifier20.402013
Novel High voltage silicon-on-insulator Device with Composite dielectric buried Layer.00.342013
An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage140.932013
ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications.00.342013
Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate00.342012
Research on periodic switching frequency modulation for conducted EMI suppressing in power converter10.362011
Purge Originator Identification TLV for IS-IS00.342011
A novel spread-spectrum clock generator for suppressing conducted EMI in switching power supply10.632010
Self-tuning PSM controller based on state machine.00.342008
A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC10.412006
A new analytical model for optimizing SOI LDMOS with step doped drift region00.342006