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XIAOLIN CHEN
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Name
Affiliation
Papers
XIAOLIN CHEN
Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany
8
Collaborators
Citations
PageRank
20
49
4.00
Referers
Referees
References
109
230
114
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100
230
Publications (8 rows)
Collaborators (20 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.
0
0.34
2015
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP
7
0.51
2015
A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing
1
0.35
2013
High-level modeling and synthesis for embedded FPGAs
3
0.40
2013
FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP
12
0.63
2012
Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors
0
0.34
2008
A design flow for architecture exploration and implementation of partially reconfigurable processors
19
0.93
2008
High-level modelling and exploration of coarse-grained re-configurable architectures
7
0.50
2008
1