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KANEMITSU OOTSU
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Name
Affiliation
Papers
KANEMITSU OOTSU
Department of Information Science, Utsunomiya University, Utsunomiya-shi, Tochigi, Japan
63
Collaborators
Citations
PageRank
66
44
23.90
Referers
Referees
References
102
586
277
Search Limit
100
586
Publications (63 rows)
Collaborators (66 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Genetic Node-Mapping Methods For Rapid Collective Communications
0
0.34
2020
Accelerating Large-Scale Interconnection Network Simulation By Cellular Automata Concept
0
0.34
2019
Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor
0
0.34
2019
Fast Computation With Efficient Object Data Distribution For Large-Scale Hologram Generation On A Multi-Gpu Cluster
0
0.34
2019
Directive-Based Parallelization of For-Loops at LLVM IR Level
0
0.34
2019
Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster.
0
0.34
2019
High level synthesis of ROS protocol interpretation and communication circuit for FPGA
0
0.34
2019
Automatic Generation Tool Of Fpga Components For Robots
1
0.41
2019
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster.
0
0.34
2018
A Genetic Approach For Accelerating Communication Performance By Node Mapping
0
0.34
2018
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster.
0
0.34
2018
Fpga Components For Integrating Fpgas Into Robot Systems
4
1.16
2018
An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives
0
0.34
2018
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA
1
0.43
2018
A Static Packet Scheduling Approach For Fast Collective Communication By Using Pso
0
0.34
2017
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus
0
0.34
2017
Acceleration Of Large-Scale Cgh Generation Using Multi-Gpu Cluster
1
0.48
2017
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component.
0
0.34
2017
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata
0
0.34
2017
A Translation Method Of Arm Machine Code To Llvm-Ir For Binary Code Parallelization And Optimization
0
0.34
2017
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration.
1
0.38
2017
Architecture exploration of intelligent robot system using ros-compliant FPGA component.
2
0.39
2016
Enhancing Entropy Throttling: New Classes Of Injection Control In Interconnection Networks
1
0.37
2016
cReComp: Automated Design Tool for ROS-Compliant FPGA Component
0
0.34
2016
Introducing PSO for Optimal Packet Scheduling of Collective Communication
0
0.34
2016
An Android Cluster System Capable Of Dynamic Node Reconfiguration
1
0.40
2015
Relaxing Heavy Congestion by State Propagation.
1
0.37
2015
Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind.
0
0.34
2015
Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU.
0
0.34
2015
Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems
0
0.34
2015
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory.
0
0.34
2015
Entropy Throttling: Towards Global Congestion Control of Interconnection Networks.
2
0.40
2015
Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations.
0
0.34
2015
Efficient Data Communication Using Dynamic Switching of Compression Method
0
0.34
2013
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History
0
0.34
2013
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind
3
0.51
2013
A Cellular Automata Approach for Large-Scale Interconnection Network Simulation
0
0.34
2013
An automatic thread decomposition approach for pipelined multithreading
0
0.34
2013
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application
0
0.34
2013
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation.
0
0.34
2013
Comparative Study of Path Prediction Method for Speculative Loop Execution
1
0.43
2012
Proposal of Incremental Software Simulation for Reduction of Evaluation Time
0
0.34
2012
Steady/Unsteady Communication Performance in Large-Scale Regular Networks
1
0.38
2011
Loop Performance Improvement for Min-cut Program Decomposition Method
1
0.35
2010
Automatic Thread Decomposition for Pipelined Multithreading
0
0.34
2010
Clustered Software Queue for Efficient Pipelined Multithreading
3
0.40
2009
An Effective Throttling Method Based on Quasi-global Congestion Information
0
0.34
2009
Are Uniform Nerworks Scalable?
0
0.34
2008
Potentials of branch predictors: from entropy viewpoints
3
0.48
2008
Clustered Decoupled Software Pipelining on Commodity CMP
3
0.38
2008
1
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