Paper Info
Title
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application
Abstract
A platform for networked FPGA system design, which is named \"ORB Engine\", is proposed to add more controllability and design productivity on FPGA-based systems composed of software and hardwired IPs. A developer can define an object-oriented interface for the circuit IP in FPGA, and implement the control sequence part using Java. The circuit IP in FPGA can be handled through object-oriented interface from variety of programing languages like C++, Java, Python, Ruby and so on. Application specific and high-efficiency circuit for ORB (Object Request Broker) protocol processing is synthesized from easy-handling Java code using JavaRock Java-to-HDL synthesizer within the de-facto standard CORBA (Common Object Request Broker Architecture). The measurement result shows a very low latency as low as 200us of UDP/IP packet in/out and exhibits a fluctuation free delay performance, which is desirable for real-time applications.
Year
DOI
Venue
2013
10.1145/2641361.2641374
SIGARCH Computer Architecture News
Keywords
Field
DocType
design,experimentation,measurement,gate arrays,performance,real-time and embedded systems
Computer science,Real-time computing,Orb (optics),Parallel computing,Common Object Request Broker Architecture,FPGA prototype,Field-programmable gate array,Object request broker,Latency (engineering),Java,Operating system,Python (programming language),Embedded system
Journal
Volume
Issue
Citations 
41
5
0
PageRank 
References 
Authors
0.34
7
5
Name
Order
Citations
PageRank
Takeshi Ohkawa12116.24
Daichi Uetake200.34
Takashi Yokota34121.70
Kanemitsu Ootsu44423.90
Takanobu Baba57127.53