Qingfeng Zhuge - Citegraph

Author Info

Name	Affiliation	Papers
QINGFENG ZHUGE	Chongqing Univ, Coll Comp Sci, Chongqing 630044, Peoples R China	21
Collaborators	Citations	PageRank
61	42	8.11
Referers	Referees	References
153	232	60

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100232

Publications (21 rows)

Collaborators (61 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices	0	0.34	2021
Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system	0	0.34	2021
SFP: Smart File-Aware Prefetching for Flash based Storage Systems	0	0.34	2021
SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives	0	0.34	2021
Performance optimization for parallel systems with shared DWM via retiming, loop scheduling, and data placement	1	0.36	2021
Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPM	0	0.34	2021
Exploring Efficient Architectures On Remote In-Memory Nvm Over Rdma	0	0.34	2021
Accommodating Transformer onto FPGA: Coupling the Balanced Model Compression and FPGA-Implementation Optimization	1	0.37	2021
Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization	0	0.34	2021
Efficient Multi-Grained Wear Leveling For Inodes Of Persistent Memory File Systems	0	0.34	2020
Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory	0	0.34	2020
Architectural Exploration on Racetrack Memories	0	0.34	2020
Latency Variation Aware Read Performance Optimization on 3D High Density NAND Flash Memory	0	0.34	2020
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search	17	0.74	2019
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference	10	0.54	2019
XFER - A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI.	3	0.44	2019
Efficient Task Assignment And Scheduling On Mpsoc With Stt-Ram Based Hybrid Spms Considering Data Allocation	0	0.34	2017
A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress	0	0.34	2017
An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks	3	0.39	2017
Area and performance co-optimization for domain wall memory in application-specific embedded systems	7	0.53	2015
Efficient Task Assignment And Scheduling For Mpsoc Dsps With Vs-Spm Considering Concurrent Accesses Through Data Allocation	0	0.34	2013