Zhifei Wang - Citegraph

Author Info

Name	Affiliation	Papers
ZHIFEI WANG	The Hong Kong University of Science and Technology	21
Collaborators	Citations	PageRank
28	27	7.86
Referers	Referees	References
74	422	154

Search Limit

100422

Publications (21 rows)

Collaborators (28 rows)

Referers (74 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition	0	0.34	2021
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning	1	0.36	2020
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems	2	0.40	2020
A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers	1	0.38	2020
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors	0	0.34	2020
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect	0	0.34	2020
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.	0	0.34	2019
Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters	0	0.34	2019
Scalable Low-Power High-Performance Rack-Scale Optical Network	0	0.34	2019
A Comprehensive Electro-Optical Model for Silicon Photonic Switches	0	0.34	2018
Rson: An Inter/Intra-Chip Silicon Photonic Network For Rack-Scale Computing Systems	0	0.34	2018
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.	2	0.38	2017
MOCA: an Inter/Intra-Chip Optical Network for Memory.	1	0.36	2017
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations	1	0.38	2016
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign	0	0.34	2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.	6	0.53	2016
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.	5	0.49	2016
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.	0	0.34	2016
Coherent crosstalk noise analyses in ring-based optical interconnects	7	0.51	2015
Adaptively tolerate power-gating-induced power/ground noise under process variations	1	0.35	2015
Alleviate chip I/O pin constraints for multicore processors through optical interconnects	0	0.34	2015