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YOONJAE CHOI
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Name
Affiliation
Papers
YOONJAE CHOI
Korea University, Seoul, Korea
8
Collaborators
Citations
PageRank
25
7
2.86
Referers
Referees
References
35
22
1
Publications (8 rows)
Collaborators (25 rows)
Referers (35 rows)
Referees (22 rows)
Title
Citations
PageRank
Year
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.
0
0.34
2022
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS
0
0.34
2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line
0
0.34
2021
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
3
0.41
2021
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
3
0.40
2019
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.
1
0.36
2018
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.
0
0.34
2018
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
0
0.34
2017
1