Paper Info
Title
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Abstract
A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes, embedded clock with dummy clock bits [1–2,5] or ensured transition density with data encoding such as 8B10B encoding [3]. However, these two schemes reduce the effective bandwidth because they require over 20% overhead in the data stream. Although highly efficient signaling schemes have been introduced recently in the literature [4] to cope with the physical limitations of the process and channel, it is difficult to adopt these multi-level signaling schemes in intra-panel interfaces where there is a highly resistive channel of Chip-On-Glass and a ground bouncing problem [5] due to different voltage domains (1V and 8V–30V) for serial link and source drivers. This paper introduces a braid clock signaling (BCS) scheme which has the following advantages: 1) clock information without redundant bits; 2) NRZ signal levels for high voltage margin; and 3) low EMI emission with a random data dependent encoding and a spread transition scheme.
Year
Venue
Field
2017
ISSCC
Clock gating,Clock drift,Clock recovery,Computer science,Clock domain crossing,Electronic engineering,Clock skew,Digital clock manager,Electrical engineering,CPU multiplier,Self-clocking signal
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
1
7
Name
Order
Citations
PageRank
Yeonho Lee153.16
Yoonjae Choi272.86
Sang-Geun Bae373.29
Jaehun Jun462.84
Junyoung Song54011.42
Sewook Hwang64110.43
Chulwoo Kim794.86