| Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS | 9 | 0.77 | 2013 |
| A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs | 0 | 0.34 | 2013 |
| A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS | 8 | 0.86 | 2012 |
| A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS | 12 | 1.05 | 2011 |
