Paper Info
Title
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
Abstract
Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.
Year
DOI
Venue
2012
10.1109/ESSCIRC.2012.6341319
european solid-state circuits conference
Keywords
Field
DocType
CMOS memory circuits,biomedical electronics,flip-flops,low-power electronics,prosthetics,CMOS,D-latch,SCM compilation flow,custom-designed standard-cell,leakage power minimisation,sensor node,silicon measurement,size 65 nm,standard-cell based memory,standard-cell based subVT memory,subVT memory compiler,subVT storage array,ultra-low power biomedical implant,voltage 220 mV
Disk array,Leakage (electronics),Computer science,Voltage,Electronic engineering,CMOS,Subthreshold conduction,Standard cell,Transistor,Electrical engineering,Low-power electronics
Conference
ISSN
ISBN
Citations 
1930-8833 E-ISBN : 978-1-4673-2211-9
978-1-4673-2211-9
8
PageRank 
References 
Authors
0.86
3
4
Name
Order
Citations
PageRank
Pascal Andreas Meinerzhagen1425.25
Andersson, O.2222.53
Mohammadi, B.3293.02
Sherazi, Y.4121.44