Name
Title | ||
|---|---|---|
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications |
Abstract | ||
|---|---|---|
The ever increasing gap between processor and memory speeds has motivated the design of embedded systems with deeper cache hierarchies. To avoid excessive miss rates, instead of using bigger cache memories and more complex cache controllers, program transformations have been proposed to reduce the amount of capacity and conflict misses. This is achieved however by complicating the memory index arithmetic code which results in performance degradation when executing the code on programmable processors with limited address capabilities. However, when these are complemented by high-level address code transformations, the overhead introduced can be largely eliminated at compile time. The clear benefits of the combined approach is illustrated on two real-life applications of industrial relevance, using popular programmable processor architectures and showing important gains in energy (a factor of 2 less) with a relatively small penalty in execution time (8-25%), instead of factors overhead without the address optimisation stage. The results of the paper leads to a systematic Pareto optimal trade-off (supported by tools) between memory power and CPU cycles which has up to now not been feasible for the targeted systems. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ISSS.2001.156541 | ISSS |
Keywords | Field | DocType |
programmable processors,limited address capability,optimisation,execution time,multimedia systems,bigger cache memory,systematic speed-power memory data-layout exploration,cache hierarchies,memory speed,high-level address code transformations,complex cache controller,cache storage,conflict misses,cache controlled embedded multimedia applications,pareto distribution,multimedia applications,systematic pareto optimal trade-off,storage allocation,memory index arithmetic code,performance degradation,miss rates,programmable processor architectures,embedded multimedia application,address capabilities,memory power,address optimisation stage,systematic speed-power memory data-layout,high-level address code transformation,real-life applications,cpu cycles,direct mapped cache,cache memories,address generation,embedded systems,program transformations,deeper cache hierarchy,industrial relevance,embedded system,control systems,arithmetic coding,indexation,processor architecture,head,cache memory,memory management,arithmetic,degradation | Uniform memory access,Cache pollution,Compile time,Cache,CPU cache,Computer science,Parallel computing,Cache algorithms,Real-time computing,Memory management,Cache coloring,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-418-5 | 6 | 0.58 |
References | Authors | |
13 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Miranda | 1 | 144 | 11.00 |
| C. Ghez | 2 | 43 | 3.76 |
| C. Kulkarni | 3 | 255 | 13.15 |
| F. Catthoor | 4 | 897 | 83.95 |
| D. Verkest | 5 | 372 | 37.99 |