Paper Info
Title
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
Abstract
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with an instruction-set processor. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A mapping flow for improving application's performance by accelerating critical software parts, called kernels, on the Coarse-Grain Reconfigurable Array is proposed. Profiling is performed for detecting critical kernel code. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. The experiments for three different instances of a generic system show that the speedup from executing kernels on the Reconfigurable Array ranges from 9.9 to 151.1, with an average value of 54.1, relative to the kernels' execution on the processor. Important overall application speedups, due to the kernels' acceleration, have been reported for the five applications. These overall performance improvements range from 1.3 to 3.7, with an average value of 2.3, relative to an all-software execution.
Year
DOI
Venue
2006
10.1109/IPDPS.2006.1639453
IPDPS
Keywords
Field
DocType
digital signal processing chips,embedded systems,instruction sets,reconfigurable architectures,system-on-chip,DSP application,coarse-grain reconfigurable logic,critical kernel code,embedded system-on-chip,instruction-set processor,priority-based mapping algorithm
Digital signal processing,System on a chip,Computer science,Instruction set,Parallel computing,Field-programmable gate array,Software,Application software,Reconfigurable computing,Speedup
Conference
ISBN
Citations 
PageRank 
1-4244-0054-6
2
0.38
References 
Authors
14
3
Name
Order
Citations
PageRank
Michalis D. Galanis19415.60
Gregory Dimitroulakos2477.14
Costas E Goutis318625.76