Name
Title | ||
|---|---|---|
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architecture |
Abstract | ||
|---|---|---|
A novel fault injection (a.k.a. fault insertion) method to facilitate the development of high quality system test is presented in this paper. In this method, we utilize the existing boundary scan (BS) architecture of an FPGA to inject a hardware fault condition at any pin of the FPGA on a circuit board. Existing user-defined instructions of most FPGA BS architectures and the newly proposed design of their corresponding user-defined scan registers (USRs) constitute the proposed fault injection architecture. No new instruction, and no modification of the existing test access port (TAP) controller and BS registers are required. In addition, it is possible to reconfigure where and what type of faults to be injected asynchronously via the BS architecture while the system is online. Although the proposed method incurs at least additional delay through a multiplexer on the pin where a fault is injected, the programmability of an FPGA enables us to add fault injection logic only to where fault injection function is desired. Hence, area overhead and performance impact can be significantly reduced. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TEST.2002.1041847 | ITC |
Keywords | Field | DocType |
boundary scan testing,design for testability,electronic equipment testing,fault simulation,field programmable gate arrays,logic design,program diagnostics,program testing,program verification,reconfigurable architectures,BS architecture user-defined instructions,BS registers,DFT,FPGA boundary scan architecture,FPGA pin hardware fault condition injection,FPGA programmability,TAP controllers,USR,area overhead/performance impact reduction,asynchronously reconfigurable fault type/location,circuit board fault injection,design-for-testability,diagnostic software test,fault injection logic,multiplexer additional delays,system test,system verification fault injection/insertion methods,test access port controllers,user-defined scan registers | Design for testing,Logic synthesis,Stuck-at fault,Boundary scan,System testing,Computer science,Field-programmable gate array,Real-time computing,Multiplexer,Electronic engineering,Fault injection,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7543-2 | 8 |
PageRank | References | Authors |
0.65 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tapan J. Chakraborty | 1 | 258 | 26.11 |
| Chen-Huan Chiang | 2 | 53 | 7.33 |