Name
Abstract | ||
|---|---|---|
In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASPDAC.2011.5722299 | ASP-DAC |
Keywords | Field | DocType |
clocks,fault simulation,flip-flops,logic testing,clock delay faults,fault simulation,flip-flops,launch-on-capture test strategy,test generation | Stuck-at fault,Automatic test pattern generation,Logic gate,Fault coverage,Computer science,Real-time computing,Electronic engineering,System time,Test strategy,Fault model,Fault indicator | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-7516-2 | 10 |
PageRank | References | Authors |
1.05 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Shin-ya Kobayashi | 3 | 38 | 8.60 |
| Kewal K. Saluja | 4 | 1483 | 141.49 |