Name
Affiliation
Papers
SHIN-YA KOBAYASHI
Ehime University, Japan
20
Collaborators
Citations 
PageRank 
10
38
8.60
Referers 
Referees 
References 
66
179
113
Search Limit
100179
Title
Citations
PageRank
Year
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.00.342016
Design And Implementation Of Data Synchronization And Offline Capabilities In Native Mobile Apps00.342016
Diagnosis of Delay Faults Considering Hazards00.342015
Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs.00.342014
Test Generation For Delay Faults On Clock Lines Under Launch-On-Capture Test Environment00.342013
Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs00.342013
Diagnosis for Bridging Faults on Clock Lines00.342012
Fault simulation and test generation for clock delay faults101.052011
On Detecting Transition Faults in the Presence of Clock Delay Faults20.382011
Enhancement of Clock Delay Faults Testing20.462011
Addressing Defect Coverage Through Generating Test Vectors For Transistor Defects00.342009
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools10.372008
Maximizing Stuck-Open Fault Coverage Using Stuck-At Test Vectors20.402008
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults70.642008
On Finding Don't Cares in Test Sequences for Sequential Circuits40.472006
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits90.742006
Generation Of Test Sequences With Low Power Dissipation For Sequential Circuits00.342004
A Method to Reduce Power Dissipation during Test for Sequential Circuits00.342002
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits10.372002
Consideration of Task’s Deadline for Scheduling Method with Used Processors Limitation00.342001