Name
Abstract | ||
|---|---|---|
A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture using a redundant number representation proposed by Kaihara and Takagi, the new architecture allows a doubled throughput due primarily to the greatly reduced critical path delay, while the area is only about 20 percent larger. Moreover, it is shown that, with a small addition to the control logic, the architecture can also be used to perform Montgomery modular multiplication, thereby efficiently realizing a unified modular multiplier/divider. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TC.2007.20 | IEEE Trans. Computers |
Keywords | Field | DocType |
plus-minus algorithm,new systolic architecture,new hardware algorithm,modular division,new architecture,control logic,area complexity,unified modular multiplier,montgomery modular multiplication,time complexity,modular multiplication,parallel algorithms,greatest common divisor,computational complexity,critical path | Cellular architecture,Modular arithmetic,Computer science,Parallel algorithm,Parallel computing,Operand,Arithmetic,Control logic,Modular design,Time complexity,Computational complexity theory | Journal |
Volume | Issue | ISSN |
56 | 2 | 0018-9340 |
Citations | PageRank | References |
4 | 0.49 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gang Chen | 1 | 4 | 0.49 |
| Guoqiang Bai | 2 | 75 | 14.56 |
| Hongyi Chen | 3 | 95 | 10.61 |