Hongyi Chen - Citegraph

Author Info

Name	Affiliation	Papers
HONGYI CHEN	Institute of Micro Electronics, Tsinghua University, Beijing, People's Republic of China 100084	20
Collaborators	Citations	PageRank
37	95	10.61
Referers	Referees	References
246	332	168

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100332

Publications (20 rows)

Collaborators (37 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
UniSec: a unified security framework with SmartNIC acceleration in public cloud	0	0.34	2019
ORTF - Open-Source Reconfigurable Testing Framework for SDN Switches.	0	0.34	2019
Malware Collusion Attack Against Machine Learning Based Methods: Issues And Countermeasures	0	0.34	2018
Bit-Precise Procedure-Modular Termination Analysis.	0	0.34	2018
BufferBank storage: an economic, scalable and universally usable in-network storage model for streaming data applications.	2	0.37	2016
Synthesising Interprocedural Bit-Precise Termination Proofs (extended version)	1	0.35	2015
Synthesising Interprocedural Bit-Precise Termination Proofs (T)	10	0.50	2015
Towards Efficient Implementation of Lattice-Based Public-Key Encryption on Modern CPUs	0	0.34	2015
A Novel Adaptive Current Biased Linear Radio-Frequency Power amplifier on SiGe HBT Process	2	0.58	2010
A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform	4	0.52	2010
An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL	18	1.23	2010
A Fast-Locking And Wide-Range Reversible Sar Dll	0	0.34	2009
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit	3	0.45	2008
Zodiac: System architecture implementation for a high-performance Network Security Processor	6	0.58	2008
A New Systolic Architecture for Modular Division	4	0.49	2007
A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit	36	1.57	2007
A Novel Unified Control Architecture for a High-Performance Network Security Accelerator	2	0.50	2007
An analog correlator for ultra-wideband receivers	0	0.34	2005
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems	0	0.34	2003
Scan array solution for testing power and testing time	7	0.77	2001