Name
Abstract | ||
|---|---|---|
In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ATS.2011.49 | Asian Test Symposium |
Keywords | Field | DocType |
integrated circuit testing,power aware,on-chip test data compression,scan-based test operation,low-power electronics,power aware embedded test,built-in self test,bist,embedded low power test,power integrated circuits,embedded systems,low power test scheme,chip,low power electronics | Automatic test pattern generation,Power integrated circuits,Computer science,Automatic test equipment,Electronic engineering,Real-time computing,Test data compression,Test compression,Low-power electronics,Built-in self-test,Embedded system | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-4577-1984-4 | 4 |
PageRank | References | Authors |
0.45 | 8 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |
| Elham Moghaddam | 2 | 79 | 7.05 |
| Nilanjan Mukherjee | 3 | 801 | 57.26 |
| Benoit Nadeau-dostie | 4 | 213 | 27.24 |
| Janusz Rajski | 5 | 2460 | 201.28 |
| Jerzy Tyszer | 6 | 838 | 74.98 |