Paper Info
Title
Combinational Logic Design Using Six-Terminal NEM Relays
Abstract
This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.
Year
DOI
Venue
2013
10.1109/TCAD.2012.2232707
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
cmos-style implementation,noelectromechanical relay-based logic circuit design,bdd-based implementation,nanotechnology,nano-electromechanical (nem) relays,six-terminal nem relays,multiple mechanical delays,bdd techniques,cmos logic circuits,multiplying circuits,combinational logic functions,binary decision diagram techniques,relay count,binary decision diagram,logic design,nanoelectromechanical devices,logic synthesis,single six-terminal relay,four-terminal relays,compact 2-to-1 multiplexer,complex logic functions,single mechanical delay,combinational logic design
Journal
32
Issue
ISSN
Citations 
5
0278-0070
15
PageRank 
References 
Authors
1.10
8
10
Name
Order
Citations
PageRank
Daesung Lee110512.96
W. Scott Lee2222.28
Chen Chen3271.81
Farzan Fallah455743.73
J. Provine5443.23
Soogine Chong6675.03
John Watkins7151.10
Roger T. Howe810315.60
H.-S. Philip Wong9645106.40
Subhasish Mitra103657228.90