Name
Title | ||
|---|---|---|
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/FPT.2011.6132670 | FPT |
Keywords | DocType | Citations |
application specific integrated circuits,clocks,digital phase locked loops,field programmable gate arrays,oscillators,synchronisation,system-on-chip,ASIC-based implementation,FPGA implementation,FPGA platform,FPGA-implemented network,all-digital phase locked loop,desirable synchronized state,digitally controlled oscillator,distributed clock generation,dynamic setup mechanism,large synchronous system-on-chip,network global synchronization,phase-frequency detector,programmable 4×4 ADPLL network,reconfigurable 4×4 ADPLL network,reconfigurable ADPLL network | Conference | 3 |
PageRank | References | Authors |
0.68 | 1 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chuan Shan | 1 | 12 | 3.55 |
| Eldar Zianbetov | 2 | 33 | 7.71 |
| Mohammad Javidan | 3 | 9 | 2.59 |
| François Anceau | 4 | 8 | 2.69 |
| Mehdi Terosiet | 5 | 6 | 5.73 |
| Sylvain Feruglio | 6 | 8 | 4.26 |
| Dimitri Galayko | 7 | 81 | 26.41 |
| Olivier Romain | 8 | 141 | 28.20 |
| Éric Colinet | 9 | 25 | 6.22 |
| Jérôme Juillard | 10 | 59 | 7.67 |