| Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. | 1 | 0.48 | 2019 |
| Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks | 1 | 0.38 | 2016 |
| Radiative Effects on MRAM-Based Non-Volatile Elementary Structures | 0 | 0.34 | 2015 |
| Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing | 0 | 0.34 | 2015 |
| A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs | 1 | 0.38 | 2015 |
| Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology | 3 | 0.45 | 2015 |
| A reconfigurable distributed architecture for clock generation in large many-core SoC | 2 | 0.43 | 2014 |
| “Swimming pool”-like distributed architecture for clock generation in large many-core SoC | 2 | 0.41 | 2014 |
| Fpga Prototyping Of Large Reconfigurable Adpll Network For Distributed Clock Generation | 2 | 0.45 | 2013 |
| Distributed clock generator for synchronous SoC using ADPLL network | 5 | 0.55 | 2013 |
| A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops. | 3 | 0.51 | 2011 |
| FPGA implementation of reconfigurable ADPLL network for distributed clock generation. | 3 | 0.68 | 2011 |
| All-digital PLL array provides reliable distributed clock for SOCs | 8 | 1.45 | 2011 |
| A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation | 2 | 0.87 | 2011 |
