Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. | 1 | 0.48 | 2019 |
“Swimming pool”-like distributed architecture for clock generation in large many-core SoC | 2 | 0.41 | 2014 |
Fpga Prototyping Of Large Reconfigurable Adpll Network For Distributed Clock Generation | 2 | 0.45 | 2013 |
On-chip clock error characterization for clock distribution system. | 0 | 0.34 | 2013 |
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. | 3 | 0.68 | 2011 |
Formal Verification: A Significant Step Towards Zero Deffect VLSI Design | 0 | 0.34 | 1989 |