Name
Title | ||
|---|---|---|
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs |
Abstract | ||
|---|---|---|
Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/988952.988999 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
bus-based socs,structured network-based design paradigm,attractive alternative,overall mp-soc,high performance socs,butterfly fat tree,soc design,specific clock cycle requirement,latest trend,clock cycle requirement,clock cycle,pipelining,bus,scalability | Butterfly fat tree,Pipeline (computing),Design paradigm,Computer science,Interconnect architecture,Real-time computing,Interconnection,Repeater,Cycles per instruction,Scalability,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-853-9 | 18 | 1.62 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cristian Grecu | 1 | 1011 | 51.04 |
| Partha Pande | 2 | 2077 | 123.22 |
| André Ivanov | 3 | 193 | 16.71 |
| Res Saleh | 4 | 292 | 16.82 |