Name
Abstract | ||
|---|---|---|
Ensuring resilience against environmental variations is becoming one of the great challenges of chip design. In this paper, we propose a self adjusting clock tree architecture, SACTA, to improve chip performance and reliability in the presence of on-chip temperature variations. SACTA performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. We present an automatic temperature adjustable skew buffer design, which enables the adaptive feature of SACTA. Furthermore, we propose an efficient and general optimization framework to determine the configuration of these special delay elements. Experimental results show that a pipeline supported by SACTA is able to prevent thermal induced timing violations within a significantly larger range of operating temperatures (enhancing the violation-free range by as much as 45°C). |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCAD.2007.4397247 | ICCAD |
Keywords | Field | DocType |
thermal induced timing violation,chip performance,skew scheduling,on-chip temperature variation,larger range,chip design,clock tree architecture,self-adjusting clock tree architecture,temperature dependent dynamic clock,adjustable skew buffer design,automatic temperature,chip,clock skew,modeling,electromagnetics,finite element method,simulation,system on chip,time domain | Time domain,Timing failure,System on a chip,Computer science,Electromagnetics,Electronic engineering,Chip,Real-time computing,Integrated circuit design,Skew,Digital clock manager | Conference |
ISSN | ISBN | Citations |
1063-6757 | 1-4244-1382-6 | 8 |
PageRank | References | Authors |
0.61 | 11 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jieyi Long | 1 | 129 | 8.98 |
| Ja Chun Ku | 2 | 59 | 6.26 |
| Seda Öǧrenci Memik | 3 | 488 | 42.57 |
| Yehea Ismail | 4 | 199 | 31.36 |